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integrated circuit systems, inc. ICSSSTUA32S869B advance information 1173?10/28/05 advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. recommended application: ddr2 memory modules provides complete ddr dimm solution with ics97u877 ideal for ddr2 400, 533 and 667 product features: 14-bit 1:2 registered buffer with parity check functionality supports sstl_18 jedec specification on data inputs and outputs 50% more dynamic driver strength than standard sstu32864 supports lvcmos switching levels on c1 and reset# inputs low voltage operation v dd = 1.7v to 1.9v available in 150 bga package green packages available 14-bit configurable registered buffer for ddr2 functionality truth table pin configuration 150 ball bga (top view) a b 12345678 9 10 11 c d e f g h j k l m n p r t u v w outputs reset# dcs# csr# ck ck# dn, dodt, dcke qn qcs# qodt, qcke h ll ll l l h ll hh l h h l l l or h l or h x q 0 q 0 q 0 h lh ll l l h lh hh l h h l h l or h l or h x q 0 q 0 q 0 h hl ll h l h hl hh h h h h l l or h l or h x q 0 q 0 q 0 hhh l q 0 hl hhh h q 0 hh h h h l or h l or h x q 0 q 0 q 0 l x or floating x or floating x or floating x or floating x or floating ll l inputs
2 ICSSSTUA32S869B advance information 1173?10/28/05 ball assignments note: nc denotes a no-connect (ball present but not connected to the die). nb indicates no ball is populated at that gridpoint. 1234567 8 91011 a nb vdd mcl (1) gnd vref gnd mcl (1) vdd b vdd nb vdd gnd nc nc nc nc gnd gnd gnd gnd vdd nb vdd c qckea vdd nb gnd nb gnd nb gnd nb vdd qckeb d q2a vdd gnd nb dcke nb d2 nb gnd vdd q2b e q3a vdd nb d3 nb nc nb dodt nb q3b f qodta vdd gnd nb nc nb nc nb gnd vdd qodtb g q5a vdd gnd d5 nb clk nb d6 gnd vdd q5b h q6a nb gnd nb nc nb nc nb gnd nb q6b j qcsa# vdd nb nc nb reset# nb csr# nb vdd qcsb# k vdd vdd gnd gnd nb nb nb gnd vdd vdd vdd l q8a vdd nb dcs# nb clk# nb d8 nb vdd q8b m q9a nb gnd nb nc nb nc nb gnd nb q9b n q10a vdd gnd d9 nb nc nb d10 gnd vdd q10b p q11a vdd gnd nb nc nb nc nb gnd vdd q11b r q12a c1 nb d11 nb nc nb d12 nb vdd q12b t q13a vdd gnd nb d13 nb d14 nb gnd vdd q13b u q14a vdd nb gnd nb gnd nb gnd nb vdd q14b v vdd nb vdd gnd gnd gnd gnd gnd vdd nb vdd w p tyerr1# vdd mcl (1) parin1 gnd vref gnd ppo1 mcl (1) vdd nb
3 ICSSSTUA32S869B advance information 1173?10/28/05 parity and standby function table reset# dcs# csr# ck ck# of inputs = h d1..? d14 (1) parin1 (2) ppo1 (2) ptyerr1# (3) hlx even l l h hlx odd l h l hlx even h h l hlx odd h l h hll even l l h hll odd l h l hll even h h l hll odd h l h hhh x x ppon 0 ptyerrn 0 # hxx l or h l or h x x ppon 0 ptyerrn 0 # l x or floating x or floating x or floating x or floating x or floating x or floating lh note 1 note 2 note 3 this transition assumes ptyerr1# is high at the crossing of ck going high and ck# going low. if ptyerr1# is low, it stays latched low for two clock cycles or until reset# is driven low. parin1 is used to generate ppo1 and ptyerr1#. inputs output inputs d1, d4 and d4 are not included in this range. parin1 arrives one (c1 = 0) or two (c = 1) clock cycles after data to which it applies.
4 ICSSSTUA32S869B advance information 1173?10/28/05 the ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 v to 1.9 v vdd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8 v cmos drivers optimized to drive the ddr2 dimm load. they provide 50% more dynamic driver strength than the standard sstu32864 outputs. the ICSSSTUA32S869B operates from a differential clock (ck and ck). data are registered at the crossing of ck going high, and ck going low. the device supports low-power standby operation. when the reset input (reset) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (vref) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs except ptyerr1# are forced low. the lvcmos reset input must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr2 rdimm application, reset is specified to be completely asynchronous with respect to ck and ck. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. ICSSSTUA32S869B must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of reset and the input receivers are fully enabled. this will ensures that there are no glitches on the output. the device monitors both dcs and csr inputs and will gate the qn, ppo1 (paritial-parity-out) and ptyerr1# (parity error) parity outputs from changing states when both dcs and csr are high. if either dcs or csr input is low, the qn, ppo1 and ptyerr1# outputs will function normally. the reset input has priority over the dcs and csr controls and will force the qn and ppo outputs low and the ptyerr1# high. the ICSSSTUA32S869B includes a parity checking function. the ICSSSTUA32S869B accepts a parity bit from the memory controller at its input pin parin1 one or two cycles after the corresponding data input, compares it with the data received on the d-inputs and indicates on its opendrain ptyerr1 pin (active low) whether a parity error has occurred. the number of cycles depends on the setting of c1, see figure 6 and 7. when used as a single device, the c1 input is tied low. when used in pairs, the c1 inputs is tied low for the first register (front) and the c1 input is tied high for the second register. when used as a single register, the ppo1 and ptyerr1# signals are produced two clock cycles after the corresponding data input. when used in pairs, the ptyerr1# signals of the first register are left floating. the ppo1 outputs of the first register are cascaded to the parin1 signals on the second register (back). the ppo1 and ptyerr1# signals of the second register are produced three clock cycles after the corresponding data input. parity implimentation and device wiring for single and dual die is described in figure 1. if an error occurs, and the ptyerr1# is driven low, it stays low for two clock cycles or until reset is driven low. the dimm-dependent signals (dcke, dcs, csr and dodt) are not included in the parity check computations. all registers used on an individual dimm must be of the same configuration, i.e single or dual die. general description ptyerr1# w1 register 1 (f ront) parin1, w4 nc, a8 pari n ppo1, w8 parin1, w4 nc, a4 register 2 (back ) nc, a8 nc, a11 set c1 = 0 for register 1; set c1 = 1 for register 2. nc denotes no connect. .. figure 1 ? parity implementation and device wiring for sstu32s869 and sstu32d869
5 ICSSSTUA32S869B advance information 1173?10/28/05 terminal functions n ote 1 inputs d1, d4 and d7 and their corresponding outputs qn are not included in this range. signal group signal name type description ungated inputs dcke, dodt sstl_18 dram funct ion pins not associated with chip select. chip select gated inputs d1 ... d14 (1) sstl_18 dram inputs, re-driven only when chip select is low. chip select inputs dc s#, csr# sstl_18 dram chip select signals. this pins initiate dram address/ command decodes, and as such at least one will be low when a valid address/command is present. re-driven outputs q1a...q14a, q1b ... q14b, qcsa#, qcsb# qckea,qckeb qodta,qodtb sstl_18 outputs of the register, vali d after the specified clock count and immediately following a rising edge of the clock. parity input parin1 sstl_18 sstl_18 inout parity is received on pin parin1 and should maintain parity across the d1...d14 (1) inputs, at the rising edge of the clock, one cycle after chip select is low. parity output ppo1 partial parity output. indicates parity out of d1-d14 (1) parity error output ptyerr1# open drain when low, this output indicates that a parity error was identified associated with the address and/or command inputs. ptyerr1# will be active for two clock cycles, and delayed by in total 2 clock cycles for compatibility with final parity out timing on the industry-standard ddr2 register with parity (in jedec definition). configuration inputs c1 1.8v lvcmos when low, register is configured as register 1. when high, register is confugured as register 2. clock inputs ck, ck# sstl_18 differential ma ster clock input pair to the register. the register operation is triggered by a rising edge on the positive clock input (ck). miscellaneous inputs reset# 1.8 v lvcmos asynchronous reset input. when low, it causes a reset of the internal latches, thereby forcing the outputs low. reset# also resets the ptyerr# signal. vref 0.9 v nominal input reference voltage for the sstl_18 inputs. two pins (internally tied together) are used for increased reliability. vdd power input power supply voltage gnd ground input groun d
6 ICSSSTUA32S869B advance information 1173?10/28/05 block diagram ck# dodt d r d r dcs# d r d r d r pari n1 d r dcke vref d1 d1 4 lsp0 internal node (cs acti ve) qodta qodt b qcsa# qcs b# qckea qckeb q14a q14b q1a q1 b 11 reset# ck csr# parity generator and checke r 2 2 2 ptye rr1# ppo1
7 ICSSSTUA32S869B advance information 1173?10/28/05 block diagram clk 2-bit counter r d clk r c1, c2 par_in 1, par_in 2 2 0 1 parity check d2 - d3, d5 - d6, d8 - d14 11 d ce clk r d2 - d3, d5 - d6, d8 - d14 v ref 11 clk# clk reset# lpso (internal node) d clk r ce d clk r ce 11 d2 - d3, d5 - d6, d8 - d14 11 11 q2a - q3a, q5a - q6a, q8a - q14a q2b - q3b, q5b - q6b, q8b - q14b ppo 1, ppo 2 2 2 ptyerr 1, ptyerr 2 0 1 d clk r note 2 parin 1 is used to generate ppo1 and ptyerr1#.
8 ICSSSTUA32S869B advance information 1173?10/28/05 register timing n + 2 n + 1 n n + 3 n + 4 reset# dcs# csr# clk clk# d1 - d14 (1) q1 - q14 (1) par_in1, (2) par_in2, ppo1, (2) ppo2 ptyerr1#, (2) ptyerr2#, note 1 this range doesn't include d1, d4 and d7 and their corresponding outputs tsu th tpd clk to q tsu th tpd clk to ppo tpd clk to ptyerr# tpd clk to ptyerr#
9 ICSSSTUA32S869B advance information 1173?10/28/05 register timing n + 2 n + 1 n n + 3 n + 4 reset# dcs# csr# clk clk# tsu th tpd clk to q tsu th tpd clk to ppo tpd clk to ptyerr# tpd clk to ptyerr# d1 - d4 q1 - q14 par_in1, par_in2 ppo1, ptyerr1#, ptyerr2# (1) (1) (2) (2) (not used) ppo2 (2) note 1: this range doesn't include d1, d4 and d7 and their corresponding outputs
10 ICSSSTUA32S869B advance information 1173?10/28/05 absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5v input voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vdd + 2.5v output voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vddq + 0.5 input clamp current . . . . . . . . . . . . . . . . . . . . 50 ma output clamp current . . . . . . . . . . . . . . . . . . . 50ma continuous output current . . . . . . . . . . . . . . . 50ma vddq or gnd current/pin . . . . . . . . . . . . . . . 100ma package thermal impedance 3 . . . . . . . . . . . . . . . 36c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only when the output is in the high state level v 0 >v ddq . 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions parameter min typ max units v dd 1.7 1.8 1.9 v re f 0.49 x v dd 0.5 x v dd 0.51 x v dd v tt v ref - 0.04 v re f v re f + 0.04 v i input voltage 0 v ddq v ih ( dc ) dc input high voltage v ref + 0.125 v ih ( ac ) ac input high voltage v ref + 0.250 v il (dc) dc input low voltage v ref - 0.125 v i l ( dc ) ac input low voltage v re f - 0.250 v ih input high voltage level 0.65 x v ddq v il input low voltage level 0.35 x v ddq v icr common mode input range 0.675 1.125 v id differential input voltage 0.600 i oh -8 i ol 8 t a 070c 1 guaranteed by design, not 100% tested in production. high-level output current data inputs ma note: reset# and cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless reset# is low. v description i/o supply voltage reference voltage operating free-air temperature reset#, c0 clk, clk# low-level output current termination voltage c1 device mode 0 first device in pair, front 1 second device in pair , back mode select
11 ICSSSTUA32S869B advance information 1173?10/28/05 electrical characteristics - dc t a = 0 - 70c; v dd = 2.5 +/-0.2v, v ddq =2.5 +/-0.2v; (unless otherwise stated) symbol parameters v ddq min typ max units v ik i i = -18ma -1.2 i oh = -100a 1.7v v ddq - 0.2 i oh = 6ma 1.7v 1.2 i ol = 100a 1.7v 0.2 i ol = 6ma 1.7v 0.5 i i all inputs v i = v d d or gnd 1.9v 5 a standb y ( static ) reset# = gnd 0.2 a operating (static) v i = v ih(ac) or v il(ac) , reset# = v d d tbd ma dynamic operating (clock only) reset# = v dd , v i = v ih(ac) or v il(ac) , clk and clk# switching 50% duty cycle. tbd /clock mhz dynamic operating (per each data input) reset# = v dd , v i = v ih(ac) or v il (ac) , clk and clk# switching 50% duty cycle. one data input switching at half clock frequency, 50% dut y c y cle tbd a/ clock mhz/data input capacitance, d n , par_in inputs v i = v ref 250 mv 2.5 3.5 pf input capacitance, dcs# n 2 3pf input capacitance, ck and ck# in p uts 2 2 3pf input capacitance, reset# in p ut v i = v dd or gnd note 2 note 2 pf data in p uts 2.5 3.5 clk and clk# 2 3 reset# 2.5 notes: 1 - guaranteed by design, not 100% tested in production. 2 - the vendor must su pp l y this value for full device descri p tion. c i v oh v ol i dd i ddd i o = 0 pf v v i = v ddq or gnd conditions v i = v ref 350mv v icr = 1.25v, v i ( pp ) = 360mv 1.8v 1.9v 1.8v v i = v ref 250 mv v icr = 0.9v; v i(pp) = 600 mv output buffer characteristics output ed g e rates over recommended operatin g free-air temperature ran g e (see fi g ure 7) min max dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt _ ? 1 1v/ns 1. difference between dv/dt_r (risin g ed g e rate) and dv/dt_f (fallin g ed g e rate) parameter v dd = 1.8v 0.1v unit
12 ICSSSTUA32S869B advance information 1173?10/28/05 timing requirements (over recommended operating free-air temperature range, unless otherwise noted) min max f clock clock frequency 340 mhz t act differential inputs active time 10 ns t inact differential inputs inactive time 15 ns t s setup time data before clk , clk# 0.5 dcs0 before clk , clk# , csr# high 0.7 hold time dcs#, dodt, dcke and q after ck , ck# 0.30 ns hold time parin1 after ck , ck# 0.30 ns 1 - guaranteed by design, not 100% tested in production. 2 - for data signal input slew rate of 1v/ns. 4 - clk/clk# signal input slew rate of 1v/ns. symbol notes: t h 3 - for data signal input slew rate of 0.5v/ns and < 1v/ns. v dd = 1.8v 0.1v units parameters ns switching characteristics (over recommended operating free-air temperature range, unless otherwise noted) symbol parameter measurement conditions min max units fmax max input clock frequency 340 mhz t pdm propagation delay, single bit switching ck to ck# qn 1.2 1.9 ns t lh low to high propagation delay ck to ck# to ptyerr# 1.2 3 ns t hl high to low propagation delay ck to ck# to ptyerr# 13ns t pdmss propagation delay simultaneous switching ck to ck# qn 2 ns t phl high to low propagation delay reset# to qn 3ns t plh low to high propagation delay reset# to ptyerr1# 3ns 1. guaranteed by design, not 100% tested in production.
13 ICSSSTUA32S869B advance information 1173?10/28/05 notes: 1. c l incluces probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma. 3. all input pulses are supplied by generators having the following chareacteristics: prr 10 mhz, zo=50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v ref = v dd /2 6. v ih = v ref + 250 mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600 mv 9. t plh and t phl are the same as t pdm . figure 6 ? parameter m easurement i nfor mation (v dd = 1.8 v 0. 1 v) r l = 1000 ? c l = 30 pf (see note 1) load circui t t w v icr v icr inpu t v ih v il voltage waveforms ? pulse durati on v ref v ref inpu t t su t h v id v icr voltage waveforms ? setup and hold time s v icr v id v ic r output v ol v oh v tt v tt t phl t plh voltage waveforms ? propagation delay time s t rphl v ol v oh v il v ih output voltage waveforms ? propagation delay times v dd /2 v tt t act t inact lv cmos input rst# voltage and current waveform s i dd (see note 2) 9 0% 10% inputs active and inactive time s 0 v v dd tes t po i n t v dd /2 v dd /2 lvcmos inp ut reset# tl=350ps, 50 ? dut ck# ou t tl t d = 350ps =50 ? ck inpu ts v id ck ck ck ck r l = 100 ? ck tes t po i n t tes t po i n t r l = 1000 ? v dd
14 ICSSSTUA32S869B advance information 1173?10/28/05 output slew rate measurement information (v dd =1.8v0.1v) all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 ; input slew rate = 1 v/ns 20%, unless otherwise specified. (1) c l includes probe and jig capacitance. figure 12 ? load circuit, high-to-low slew measurement figure 13 ? voltage waveforms, high-to-low slew rate measurement (1) c l includes probe and jig capacitance. figure 14 ? load circuit, low-to-high slew measurement figure 15 ? voltage waveforms, low-to-high slew rate measurement c l = 10 pf see note (1) v dd out dut test point r l = 50 ? 002aaa377 v oh v ol output 80% 20% dv_f dt_f 002aaa378 c l = 10 pf see note (1) out dut test point r l = 50 ? 002aaa37 9 v oh v ol 80% 20% dv_r dt_r output 002aaa380
15 ICSSSTUA32S869B advance information 1173?10/28/05 error output load circuit and voltage measurement information (v dd =1.8v0.1v) all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 ; input slew rate = 1 v/ns 20%, unless otherwise specified. (1) c l includes probe and jig capacitance. figure 16 ? load circuit, error output measurements figure 17 ? voltage waveforms, open-drain output low-to-high transition time with respect to reset# input figure 18 ? voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs figure 19 ? voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs c l = 10 pf see note (1) v dd out dut test point r l = 1 k 002aaa500 v cc /2 t plh v cc 0 v 0.15 v v oh 0 v output waveform 2 lvcmos reset input 002aaa501 v icr t hl v cc /2 v cc v ol timing inputs output waveform 1 v i(pp) v icr 002aaa502 v icr t lh v oh 0 v timing inputs output waveform 2 v i(pp) v icr 0.15 v 002aaa503
16 ICSSSTUA32S869B advance information 1173?10/28/05 (1) c l includes probe and jig capacitance. figure 22 ? partial parity out load circuit v tt = v dd /2 v icr cross point voltage v i(p-p) = 600mv t plh and t phl are the same as t pd . figure 23 ? partial parity out voltage wavefor m, propagation delay time with respect to clk input r l =1k c l =5pf dut out tes t po i n t see note (1 ) ck ck t plh t phl v icr v icr v i(p-p) v tt output v tt
17 ICSSSTUA32S869B advance information 1173?10/28/05 ics xxxx y h (lf)- t ordering information ICSSSTUA32S869Bh(lf)-t example: designation for tape and reel packaging lead free, rohs compliant (optional) package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device d e t e horiz vert total d h d1 e1 b c min/max min/max min/max 13.00 bsc 8.00 bsc 0.90/1.20 0.65 bsc 11 19 150 0.38/0.48 0.27/0.37 11.70 bsc 6.50 bsc 0.65 0.75 *** all dimensio ns in millimeters ref. dims ----- ball grid ----- note: ball grid total indicates maximum ball count for package. lesser quantity may be used. d1 d= e1 b c d h= e t
18 ICSSSTUA32S869B advance information 1173?10/28/05 revision history rev. issue date description page # 0.1 10/27/2005 initial release. -

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